1. Field of the Invention
The present invention relates to transistors, transistor arrays, methods of manufacturing transistor arrays, and to nonvolatile semiconductor memories.
2. Description of the Related Art
Nonvolatile semiconductor memories such as FeRAM (Ferro-electric Random Access memory), EPROM (Erasable and Programmable Read Only Memory), and EEPROM (Electrically Erasable and Programmable Read Only Memory) are currently attracting attention. EPROMs and EEPROMs store data by storing an electrical charge at a floating gate and then using a control gate to detect changes in a threshold voltage thereof due to the presence or absence of an electrical charge. One current EEPROM is an EEPROM which erases data in a unit of a complete memory chip, and another is a flash EEPROM which divides memory cell arrays thereof into arbitrary blocks and data erasing is carried out for each block.
Flash EEPROMs have advantages such as (1) non-volatility of stored data, (2) low power consumption, (3) capability of electrical rewriting (on-board rewriting), and (4) low cost. Therefore, their range of application has been spreading to include storage memories for programs or data used in cellular phones and mobile information terminals.
Memory cells which constitute flash EEPROMs have several types including split gate and stacked gate types.
In a flash EEPROM which uses stacked gate type memory cells, memory an cells do not have a self-selection function. Therefore, when an electric charge is over-discharged from a floating gate electrode while erasing data, a channel region will become ON, even when a predetermined voltage for an OFF state (e.g., 0V) is applied to a control gate electrode. As a consequence, memory cells are continually kept in an ON state, and a problem that reading stored data becomes impossible, that is, a so-called over-erase problem, occurs. To prevent over-erase from occurring, processing is necessary in an erasing operation such as controlling erasing operation at a peripheral circuit of a memory device or at an external circuit thereof.
To prevent over-erase in stacked gate type memory cells, split-type memory cells have been developed.
A flash EEPROM using split-type gate memory cells has been disclosed in WO92/18980 (G11C 13/00).
FIG. 19 is a cross-section of a conventional split gate type memory cell 201.
The split gate type memory cell 201 (split gate type transistor) comprises a source region 203, drain region 204, a channel region 205, a floating gate electrode 206, and a control gate electrode 207.
The N type source region 203 and drain region 204 are formed on a P type monocrystalline silicone substrate. Over the channel region 205 which lies between the source region 203 and the drain region 204, the floating gate electrode is formed with a gate insulating layer 208 covering the channel region 205 and the floating gate electrode 206. The control gate electrode 207 is formed over the floating gate electrode 206 which is covered by an insulating layer 209 made by LOCOS (Local Oxidation of Silicon) method, with an insulating layer 210 lying between the floating gate electrode 206 and the control gate electrode 207. As it is covered with the insulating layer 209, the floating gate electrode has two protuberances 206a in an upper portion thereof.
A portion of the control gate electrode 207 lies over the channel region 205 with the insulating layers 208 and 210 lying between the portion of the control gate 207 and the channel region 205, and forms a selecting gate 211. A selecting transistor 212 is formed with the selecting gate 211, the source region 203, and the drain region 204. In other words, the split gate type memory cell 201 comprises the selecting transistor 212 and transistors which comprise the floating gate electrode 206, the control gate electrode 207, the source region 203, and the drain region 204, the aforesaid transistors being laid out in series.
FIG. 20a is a partial cross section of a memory cell array 302 included in a flash EEPROM 301 using the split gate type memory cells 201.
The memory cell array 302 comprises a plurality of memory cells 201 formed on a silicon substrate 202.
To keep the region occupied on the silicon substrate 202 small, two memory cells 201 (hereafter called 201a and 201b for distinction) share the source region 203, and the floating gate electrodes 206 and the control gate electrodes 207 are lad out symmetrically around the common source region 203.
FIG. 20b is a partial top view of the memory cell array 302. FIG. 20a is the cross section of the memory cell array 302 cut by the line X--X shown in FIG. 20b.
A field insulating layer 213 is formed on the silicon substrate 202, and the field insulating layer separates elements of each memory cell 201. Each source region 203 laid out vertically in FIG. 20b is shared. Also, each control gate electrode 207 of each memory cell 201, the control gate electrode being laid out vertically in FIG. 20b, is shared. Each control gate electrode forms a word line. Each drain region 204 laid out horizontally in FIG. 20b is connected to a bit line (not shown) via a bit line contact 214.
FIG. 21 shows an entire configuration of the flash EPROM 301 using split gate type memory cells 201.
The memory cell array 302 is configured with a plurality of memory cells 201 laid out to form a matrix. The control gate electrodes 207 which are laid out in rows form common word lines WL1-WLn. The drain regions 204 of memory cells 201 are laid out in columns and connected to common bit lines BL1-BLn.
Each memory cell 201b connected to a word line with an odd number (WL1, WL3, . . . WLm . . . WLn-1) shares the source region 203 with each memory cell 201a connected to a word line with an even number (WL2, WL4, . . . WLm+1 . . . WLn). The shared source region 203 forms each source line RSL1-RSLm-RSLn. For example, the memory cell 201b which is connected to a word line WLm and the memory cell 201a which is connected to a word line WLm+1 share the source region 203, while the shared source region 203 forms a source line RSLm. Each source line RSL1-RSLn is connected to a common source line SL.
Each word line WL1-WLn is connected to a row decoder 303, while each bit line BL1-BLn is connected to a column decoder 304.
Row and column addresses specified by an external source are input to an address pin 305. The row address and column address are transferred from the address pin 305 to an address latch 307 via an address buffer 306. Among the addresses latched by the address latch 307, the row address is transferred to the row decoder 303, while the column address is transferred to the column decoder 304.
The row decoder 303 selects a word line which corresponds to the row address latched by the address latch 307 (for example, WLm), and controls a voltage of each word line WL1-WLn corresponding to a later-described operation mode. In other words, by controlling the voltage of each word line WL1-WLn, a voltage of each control gate electrode 207 in each memory cell 201 is controlled.
The column decoder 304 selects a word line which corresponds to the column address latched by the address latch 307 (for example, BLm), and controls a voltage of each bit line BL1-BLn corresponding to a later-described operation mode. In other words, the voltage of each drain region 204 in each memory cell 201 is controlled by controlling the voltage of each bit line BL1-BLn.
The common source line SL is connected to a bias circuit 312. The source line bias circuit 312 controls, via the common source line SL, a voltage of each source line SL1-SLn corresponding to each later-described operation mode. In other words, by controlling the voltage of each source line SL1-SLn, the voltage of each source region 203 in each memory cell 201 is controlled.
Data specified by an external source is input to data pin 308. The data is transferred from the data pin 308 to the column decoder 304 via an input buffer 309. The column decoder 304 controls the voltage of each bit line BL1-BLn corresponding to the data, as will be described later.
Data read from any memory cell 201 is transferred from the bit line BL1-BLn to a sense amplifier 310 via the column decoder 304. The sense amplifier 310 is a current sense amplifier. The column decoder 304 connects one bit line BL1-BLn which the column decoder selects with the sense amplifier 310. The distinguished data by the sense amplifier 310 is output from an output buffer 311 to outside via the data pin 308.
The above-described operations of each circuit (303-312) are controlled by a control core circuit 313.
Each operation mode of the flash EEPROM 301 (writing, reading, and erasing) will be described hereinbelow referring to FIG. 22.
(a) Writing Operation (See FIG. 22a)
The drain region of the selected memory cell 201 is grounded via a constant current source 310a set within the sense amplifier 310. The voltage of the drain region is set to 1.2 V. The voltage of each drain region of the memory cells 201 which are not selected is set to 3 V.
The voltage of the control gate electrode 207 of the selected memory cell 201 is set to 2 V. The voltage of each control gate electrode of the memory cells 201 which are not selected is set to 0 V.
The voltages of all source regions 203 in all memory cells 201 are set to 12 V.
In the memory cell 201, a threshold voltage Vth of the selecting transistor 212 is approximately 0.5 V. Therefore, in the selected memory cell 201, electrons in the drain region 204 move to the channel region 205 in an inversion state. As a result, a cell current flows from the source region 203 to the drain region 204. On the other hand, the voltage of the source region is 12 V. Therefore, coupling through a capacity between the source region 203 and the floating gate electrode 206 raises the potential of the floating gate electrode closer to 12 V. As a consequence, a high potential field is created between the channel region 205 and the floating gate electrode 206. Therefore, electrons in the channel region 205 are accelerated to become hot electrons, and are injected to the floating gate electrode 206, as shown by an arrow A in FIG. 22a. As a result, electric charge is accumulated in the floating gate electrode 206 in the selected memory cell 201, and 1 bit data is thus written and stored.
This writing operation is carried out by each selected memory cell 201.
(b) Reading Operation (See FIG. 22b)
The potential of the drain region of the selected memory cell 201 is set to 2 V. The potentials of the drain regions 204 of the memory cells 201 which are not selected are set to 0 V.
The potential of the control gate electrode 207 of the selected memory cell 201 is set to 4V. The potentials of the control gate electrodes 207 of the memory cells 201 which are not selected are set to 0 V.
The potentials of the source regions 203 of the all memory cells 201 are set to 0 V.
As will be described later, electric charge is not stored in an erasing mode of the floating gate electrode 206 in the memory cell 201. On the other hand, as described above, electric charge is stored in the writing mode in the floating gate electrode 206 of the memory cell 201. Therefore, the channel region 205 under the floating gate electrode 206 of the memory cell 201 in the erasing mode is in an ON state, while the channel region 205 under the floating gate electrode 206 of the memory cell 201 in the writing mode is in an OFF state. As a consequence, when 4 V is applied to the control gate electrode 207 , the cell current, which flows from the drain region 204 to the source region 203, becomes larger in the memory cell 201 in the erasing mode than the memory cell 201 in the writing mode.
By distinguishing the magnitude of the cell current between each memory cell 201 using the sense amplifier 310, data stored in the memory cell 201 can be read. For example, reading is performed by setting the data value in the memory cell 201 to 1, the erasing mode, and by setting the data value of the memory cell 201 to 0, the writing mode. In other words, each memory cell 201 is forced to store one of the two values 1, which is the data value in the erasing mode, or 0, which is the data value in the writing mode, and the data value stored can be read.
(c) Erasing Operation (See FIG. 22c)
The potentials of the drain regions 204 of all memory cells 201 are set to 0 V.
The potential of the control gate electrode 207 of the selected memory cell 201 is set to 15 V. The potentials of the control gate electrodes 207 of the memory cells 201 which are not selected are set to 0 V.
The potentials of the source regions 203 of all memory cells 201 are set to 0 V.
The capacity between the source region 203/silicon substrate 202 and the floating gate electrode 206 is far greater than the capacity between the control gate electrode 207 and the floating gate electrode 206. In other words, the floating gate electrode 206 is strongly coupled with the source region 203 and the silicon substrate 202. Therefore, if the voltages of the control gate electrode 207 and the drain region 204 become 15 V and 0 V respectively, the voltage of the floating gate electrode does not change greatly from the 0 V. As a result, the potential difference between the control gate electrode 207 and the floating gate electrode 206 becomes larger, and a high potential field is created between the control gate electrode 207 and the floating gate electrode 206.
As a consequence, a Fowler-Nordheim Tunnel Current (hereafter called FN tunnel current) flows. Therefore, as shown by an arrow B in FIG. 22c, electrons in the floating gate electrode 206 are pulled toward the control gate electrode 207, and the data stored in the memory cell 201 is erased.
At this time, since the floating gate electrode 206 has protuberances 206a, the electrons in the floating gate electrode 206 rush out of the protuberances 206a, and move to the control gate 207. Therefore, the movement of the electrons become easier, and the electrons in the floating gate electrode 206 are effectively pulled out.
The control gate electrodes 207 in memory cells 201 which are laid out in columns form common word lines WL1-WLn. Therefore, erasing operation is carried out on all memory cells 201 connected to the selected word line WLn.
By simultaneously selecting a plurality of word lines WL1-WLn, all memory cells 201 connected to the selected word lines can be erased. As described above, an erasing operation by dividing memory cell arrays 302 into block units composed of a plurality of word lines WL1-WLn and then erasing data by each block is called block erasing.
A flash EEPROM 301 using split gate type memory cells 201, with the memory cells 201 being composed as described above, includes selecting transistors 212. Therefore, each memory cell 201 has a function to select itself. In other words, if the electrical charge is pulled out excessively from the floating gate electrode 206 when data is erased, the selecting gate 211 can set the channel region 205 to an OFF state. Therefore, even when an over erasing occurs, the selecting transistor 212 can control ON and OFF states of the memory cell, and over erasing problems do not occur. In other words ON or OFF state of the memory cell can be selected by the selecting transistor 212 set within the memory cell 201.
A method to produce the memory cell array 302 will be explained sequentially hereinbelow.
Step 1 (See FIG. 23a): Using the LOCOS method, the field insulating layer 213 (not shown) is formed on the silicon substrate 202. The gate insulating layer 208 which is composed of a silicon oxide layer is then formed, using a thermal oxidation method, on portions of the silicon substrate 202 where no field insulating layer 213 is formed (element regions). On the gate insulating layer 208, a doped polysilicon layer 215 which will become the floating gate electrode 206 is formed. Using an LPCVD method (Low Pressure Chemical Vapor Deposition), a silicon nitride layer 216 is then formed on the entire surface of the doped polysilicon layer 215. A photoresist coats the silicon nitride layer 216, and then an etching mask 217 to be used for the floating gate electrode 206 is formed using an ordinary photo lithography technique.
Step 2 (See FIG. 23b): The silicon nitride layer 216 is etched by anisotropy etching using the etching mask 217. The etching mask 217 is then detached. Using the LOCOS method, by oxidizing the doped polysilicon layer 215 using the etched silicon nitride layer 216 as an oxide mask, the insulating layer 209 is formed. At this time, edge portions of the insulating layer 209 intrude edge portions of the silicon nitride layer 216, and form bird's beaks 209a.
Step 3 (See FIG. 23c): The silicon nitride layer 216 is removed. The doped polysilicon layer 215 is etched by the anisotropy etching using the insulating layer 209 as the etching mask to form the floating gate electrodes 206. As bird's beaks 209a are formed on the edge portions of the insulating layer 209, the upper edge portions of the floating gate electrodes 206 become sharp, and form protuberances 206a.
Step 4 (See FIG. 23d): The insulating layer 210 composed of a silicon oxide layer is formed on the entire surface of the device composed as described above by the thermal oxidation method, or the LPCVD method, or a combination thereof. The stacked insulating layer 208 is unified with the insulating layer 210, and the insulating layer 209 is also unified with the insulating layer 210.
Step 5 (See FIG. 24e): On the entire surface of the device formed through the above-described steps, a doped polysilicon layer 218 which will become the control gate electrode 207 is formed.
Step 6 (See FIG. 24f): After photoresist coating on the entire surface of the device as described above, an etching mask 219, which will be used to form the control gate electrode 207, is formed using the ordinary photo lithography technique.
Step 7 (See FIG. 24g): The doped polysilicon layer 218 is etched and forms control gate electrodes 207 by the anisotropy etching using the etching mask 219. The etching mask 219 is then removed.
Step 8 (See FIG. 25h): After photoresist coating on the entire surface of the device through the above steps, a mask for ion injection 220 which will be used to form the source regions 203 is formed using the ordinary photo lithography technique. Using an ordinary ion injection method, phosphorous ions (p.sup.+) are injected on the surface of the silicon substrate 202 so that source regions 203 are formed. The mask for ion injection 220 is then removed.
At this time, the mask for ion injection 220 should be formed so that it covers at least the regions on the silicon substrate 202, which will become the drain regions 204. The mask for the ion injection 220 should also be formed not to protrude beyond the floating gate electrodes 206. As a result, positions of the source region 203 are defined by the edge portions of the floating gate electrodes 206.
Step 9 (See FIG. 25i): After photoresist coating on the entire surface of the device as composed through the above-described steps, a mask for ion injection 221 which will be used to form the drain regions 204 is formed using the ordinary photo lithography technique. Using an ordinary ion injection method, arsenic ions (As.sup.+) are injected on the surface of the silicon substrate 202 so that drain regions 204 are formed.
The mask for ion injection 221 should then be formed so as to cover at least the source regions 203 and so as not to protrude beyond the control gate electrodes 207. As a result, positions of the drain regions 204 are defined by the edge portions of the control gate electrodes 207 on the selecting gate 211 side.
After the mask for ion injection 221 is removed, the memory cell array 302 is completed.
Flash EEPROMs 301 using the split gate type memory cells 201 have the following problems.
(1) Due to misalignment of the etching mask 219 which will be used for forming the control gate electrodes 207, a fluctuation in writing characteristic of each memory cell 201 occurs.
As shown in FIG. 26a, in the above-described step 6, if the relative positions of the etching mask 219, which will be used to form the control gate electrodes 207, to the memory cells 201a and 201b are shifted from the originally designed position, the shapes of the control gate electrodes 207 formed in step 7 above will not be the same for memory cells 201a and 201b.
When the drain regions are formed in the above-described step 9 by the ion injection method, the positions of the drain regions 204 are defined by the edge portions of the control gate in the selecting gate 211 side.
Therefore, as shown by FIG. 26a, if the position of the etching mask 219 is shifted from the originally designed position, length L1 and L2 of the channel regions 205 (channel length) of the memory cells 201a and 201b are not the same as shown by FIG. 26b. However, even though the position of the etching mask 219 is shifted from the originally designed position, the width of the mask does not change. Thus, even though the shapes of the control gate electrodes 207 are not the same, the width of the control gate electrodes remains constant. For example, if the position of the etching mask 219 is shifted toward the memory cell 201b, the channel length L2 of the memory cell 201b is shorter then the channel length L1 of the memory cell 201a.
If channel length L1 and L2 differ, the resistance of the channel regions 205 will likewise differ. Therefore, cell current values will also be different in the writing operation. In other words, a longer channel length will result in larger resistance of the channel region 205, and smaller cell currents in the writing operation. If the cell currents which flow in the writing operation offer, the rate of hot electron generation will also differ. As a result, writing characteristics of the memory cells 201a and 201b will also differ.
(2) To prevent the problems described in (1), compacting memory cell 201 is hindered.
When designing the split gate type memory cell 201, alignment accuracy of each gate electrode 206 or 207 should be considered as well as patterning rule accuracy. Taking these factors into consideration, gate electrodes 206 and 207, and channel regions 203 and 204 should be positioned with some free space therebetween. However, in current production techniques of high density semiconductors, when an approximately 0.5 .mu./m wide line is processed, the patterning rule accuracy can be up to 0.05 .mu.m, while the alignment accuracy is up to 0.1-0.2 .mu.m. In other words, in the split gate type memory cell 201, the alignment accuracy of gate electrodes 206 or 207 prevents compacting the memory cell 201.
(3) The split gate type memory cell 201 is more difficult to compact than a stacked gate type memory cell.
In a stacked gate type memory cell, widths of both floating gate and control gate electrodes are equivalent, and both gate electrodes are stacked without a position shift. On the other hand, in the split gate type memory cell 201, one portion of the control gate electrode 207 is laid out over the channel region 205 so that they form the selecting gate 211. Therefore, in the split gate type memory cell 201, the occupied area of the elements is larger by the area of the selecting gate 211 than in the stacked gate type memory cell. In other words, even though split gate type memory cells do not have problems with over erase, they are more difficult in higher integration than stacked gate type memory cells, due to the problems described in (2) and (3).
(4) The memory cell array 302 using the split gate type memory cell 201 is complex in structure and time consuming to produce.